NVIDIA Rubin Architecture: What Comes After Blackwell Will Change Everything
Every data center that runs air cooling today is already obsolete for NVIDIA's next platform. The Rubin GPU — now confirmed in full production with volume shipments beginning the second half of 2026 — draws between 1,800 and 2,300 watts per chip. No fan array handles that. No raised-floor plenum redirects it. Facilities without direct-to-chip liquid cooling cannot host Rubin at all, regardless of available power capacity. This is not a caveat buried in a spec sheet. It is the clearest statement NVIDIA has ever made about who gets access to the next generation of AI compute — and who gets left behind.
Most coverage of Rubin focuses on the headline numbers: 50 petaflops of FP4 inference per GPU, 336 billion transistors, HBM4 memory at 22 terabytes per second. Those figures are real and they matter. What most coverage skips past is what they cost — in watts, in capital, in supply chain realities that are already bending the deployment timelines of organizations that thought they were prepared. The gap between NVIDIA's performance roadmap and the physical infrastructure required to run it has never been wider, and almost no one outside the hyperscaler tier is talking about it honestly.
This article traces what Rubin actually delivers at the chip and rack level, where its claimed 10x inference cost reduction holds and where it does not, how AMD's Helios platform competes on the specific numbers that matter, and what the architecture's trajectory from Rubin Ultra in 2027 to Feynman in 2028 means for procurement decisions being made right now.
- The Architecture: Six Chips, One Platform
- HBM4, NVLink 6, and the Memory Bandwidth Leap
- The 10x Inference Claim — What the Benchmark Actually Measures
- Power, Cooling, and the Liquid Infrastructure Mandate
- AMD Helios MI455X: Where the Competition Actually Leads
- The Roadmap Beyond Rubin: Ultra, Feynman, and the Annual Cadence
- Geopolitics and the China Market
- Who This Is For
- Verdict
- Frequently Asked Questions
The Architecture: Six Chips, One Platform
NVIDIA announced Rubin in full production at CES 2026, months ahead of what analysts had expected. The platform is not a GPU. It is six co-designed chips — the Rubin GPU, the Vera CPU, NVLink 6 Switch, ConnectX-9 SuperNIC, BlueField-4 DPU, and Spectrum-6 Ethernet switch — shipped as a single integrated system. Every data path inside a Vera Rubin rack runs on NVIDIA-designed silicon from the same architectural generation.
At the center sits the Rubin GPU, designated VR200. VideoCardz confirmed the chip carries 336 billion transistors across two reticle dies, 288 GB of HBM4 per package, and up to 50 petaflops of NVFP4 inference — framed by NVIDIA as 5x over Blackwell's 10 petaflops. The manufacturing process is TSMC's 3nm node, using CoWoS-L advanced packaging to stitch the two compute dies together. NVIDIA is using Blackwell GPUs to accelerate the design of Vera, Rubin, and Rubin's successor Feynman — a recursion that will become relevant again when the cadence discussion arrives.
The Vera CPU pairs with Rubin in a single superchip package. Vera carries 88 custom ARM "Olympus" cores running 176 threads via Spatial Multi-Threading, with up to 1.5 TB of LPDDR5x and 1.2 TB/s of memory bandwidth. The coherent NVLink-C2C interface between Vera and the Rubin dies runs at 1.8 TB/s — a dedicated lane that eliminates the PCIe bottleneck that has degraded CPU-GPU communication in every previous generation. For KV cache management and prefill operations in large language model inference, this bandwidth figure is the one that actually determines whether a model fits in the context window without spilling to slower memory.
The flagship rack configuration — the Vera Rubin NVL72 — packs 72 Rubin GPUs and 36 Vera CPUs into a single NVLink 6 domain. Aggregate NVLink bandwidth across the rack: 260 TB/s. NVIDIA's claim is that this exceeds the total bandwidth of the entire public internet.
HBM4, NVLink 6, and the Memory Bandwidth Leap
Memory bandwidth is the ceiling that determines which AI workloads are economically viable, and HBM4 in Rubin represents the sharpest generational jump in this metric since the Volta-to-Ampere transition. Each Rubin GPU carries 288 GB of HBM4 across eight stacks delivering 22 TB/s of bandwidth — 2.8x over Blackwell's 8 TB/s and 6.6x over the H100's 3.35 TB/s. NVIDIA achieved this by pushing HBM4 pin speeds to over 11 Gbps per pin on 8-Hi stacks, exceeding the JEDEC specification. The final figure of 22.2 TB/s was not in the original GTC 2025 announcement: NVIDIA raised the spec by 10% at CES 2026 specifically to stay ahead of AMD's MI455X, which uses 12-Hi HBM4 stacks to reach 19.6 TB/s.
NVLink 6 doubles the per-GPU interconnect bandwidth from NVLink 5's 1.8 TB/s to 3.6 TB/s bidirectional. For Mixture of Experts (MoE) model workloads — where over 60% of open-source model releases in 2025 used MoE architectures according to Barrack AI's technical breakdown — the all-to-all GPU communication pattern is the primary bottleneck. A doubling of interconnect bandwidth directly reduces gradient sync time for communication-bound training runs. NVIDIA's 260 TB/s NVLink 6 fabric across a NVL72 rack compares to AMD's UALink-over-Ethernet implementation, which ships in the initial Helios release rather than native UALink silicon — a distinction with real consequences for distributed training efficiency.
HBM4 doubles the interface width per stack to 2,048 bits, compared to HBM3e's 1,024 bits. That architectural change is what makes the bandwidth jump possible without simply stacking more silicon. The practical effect for model serving: a 70-billion-parameter model that previously required multi-GPU tensor parallelism can potentially run on fewer Rubin GPUs, reducing the communication overhead that parallelism introduces.
The 10x Inference Claim — What the Benchmark Actually Measures
NVIDIA's most-cited Rubin claim is a 10x reduction in inference token cost versus Blackwell. The number has appeared in every GTC 2026 slide and every press release. It deserves narrower framing than it usually gets.
"NVIDIA's 10x figure is benchmarked on the Kimi-K2-Thinking model at 32K input / 8K output sequence lengths, comparing the Vera Rubin NVL72 against the GB200 NVL72. It is a specific MoE model at specific sequence lengths on a specific system configuration."
This is not a general-purpose 10x improvement across all workloads. MoE models see outsized gains from Rubin because their all-to-all communication patterns map directly onto NVLink 6's fabric strengths. Dense transformer models, smaller fine-tuned models, and batch inference workloads at different sequence lengths will see different ratios. The 10x figure is real for the workload it measures. Teams running dense encoder-decoder models at shorter context lengths should plan for gains closer to the 3x-5x range implied by the raw FP4 compute improvement from Blackwell to Rubin.
For agentic AI, the math changes materially. Multi-step reasoning generates roughly 5x more tokens per request than single-turn inference. At Blackwell-era token pricing, running an agent that chains 10 reasoning steps was prohibitively expensive for most startups at consumer scale. At Rubin-projected pricing for MoE models, the economics shift enough to make it viable. That specific transition — from agent prototypes to agent products — is what hyperscalers with confirmed Rubin deployments are actually positioning for, not the headline benchmark.
The number nobody uses: Each HBM4 stack in a Rubin GPU may dissipate 20-30 watts — compared to 15-20 watts for HBM3e. With 8-12 stacks per GPU, cooling the memory alone requires a cold plate capable of managing both a concentrated high-flux GPU die and a distributed ring of moderate-flux memory stacks simultaneously. Asymmetric cold plate designs with zone-optimized channels are required. This is not a thermal curiosity; it is an engineering constraint that is adding months to data center commissioning schedules.
Power, Cooling, and the Liquid Infrastructure Mandate
Rubin operates at 1,800 to 2,300 watts per GPU. Blackwell ran at 1,000 watts. That difference is not additive; it is categorical. Every Rubin system requires 100% direct-to-chip liquid cooling — no air-cooled configuration exists or is planned. The VR200 NVL72 rack draws 190-230 kilowatts, up from 120-130 kilowatts for Blackwell NVL72. The 2027 Rubin Ultra "Kyber" rack is specified at approximately 600 kilowatts.
For data center operators, the practical effect is binary. Facilities without liquid cooling infrastructure cannot host Rubin regardless of available power capacity. Retrofitting an air-cooled facility for Rubin-class density requires 6 to 12 months of construction and capital outlay measured in millions of dollars per megawatt of converted capacity, per Introl's analysis of CES 2026 disclosures. Specific retrofit cost range: $500 to $1,500 per kilowatt depending on existing infrastructure — meaning $60,000 to $195,000 per Rubin rack for cooling alone, before touching the compute hardware.
Rubin also introduces 800V DC power architecture, a departure from the 48V distribution standard in prior data center designs. This requires new power distribution hardware throughout the facility, not just new cooling. Organizations that began liquid cooling investment in 2024-2025 hold a timing advantage that cannot be manufactured quickly by those who did not.
You have just committed budget to a Rubin deployment and your facilities team tells you the liquid cooling retrofit will not complete until Q2 2027. You now own an allocation of hardware that cannot ship anywhere on your site. That is not a hypothetical. It is what is happening to multiple enterprise buyers right now, and NVIDIA's allocation queue means you cannot simply return your slot to the market.
Production ceiling for 2026 is estimated at 200,000 to 300,000 Rubin GPUs total, constrained by TSMC's N3 advanced packaging capacity and HBM4 supply from SK Hynix and Samsung, who began HBM4 mass production in Q4 2025 with yields still below mature HBM3e levels. SK Hynix delayed plans to ramp HBM4 production from Q2 to Q3 2026, favoring gradual ramp-up to protect its HBM3e business for existing Blackwell customers. Reports from SDxCentral note additional challenges in the ConnectX-8 to ConnectX-9 NIC transition, which could affect complete system availability timelines independent of GPU supply.
AMD Helios MI455X: Where the Competition Actually Leads
AMD's Helios platform — 72 MI455X accelerators in a rack-scale configuration unveiled at CES 2026 — is the first direct challenge to NVIDIA's NVL72 that deserves the label. The per-chip comparison shows NVIDIA leading on FP4 compute (50 PFLOPS vs. 40 PFLOPS) and memory bandwidth (22 TB/s vs. 19.6 TB/s). AMD leads on raw memory capacity per chip: 432 GB of HBM4 versus Rubin's 288 GB — 50% more, using 12-Hi stacks. At the rack level, KAD's comparison shows AMD's Helios carrying 31 TB of HBM4 against the Vera Rubin NVL72's 20.7 TB.
That memory capacity gap is not a rounding error. Large language models and multimodal systems at frontier scale require memory headroom for parameters, KV cache, and activation tensors simultaneously. A system with 50% more memory per GPU can serve larger models without tensor parallelism across multiple chips, which lowers communication overhead and reduces latency. For organizations running models above 200 billion parameters in production without tensor parallelism, Helios may actually outperform Rubin in specific configurations.
AMD's pricing positions Helios at 15-25% below comparable NVIDIA systems. Per-GPU cost estimates from X's technical community put AMD at $35,000-$40,000 versus NVIDIA's $55,000-$65,000 per GPU. The software gap — ROCm 8 versus CUDA — remains AMD's structural disadvantage. Most production ML frameworks are built against CUDA primitives, and ROCm's compatibility layer introduces performance unpredictability on workloads that depend on fused CUDA kernels not yet ported to the AMD stack. AMD's first Helios release also ships UALink-over-Ethernet rather than native UALink silicon, meaning large-scale distributed training efficiency carries uncertainty until native interconnect hardware ships.
The competition is real. It is also narrower than AMD's headline numbers suggest.
The Roadmap Beyond Rubin: Ultra, Feynman, and the Annual Cadence
NVIDIA has committed to an annual architecture cadence through at least 2028: Rubin in H2 2026, Rubin Ultra in H2 2027, Feynman in 2028. Rosa Feynman appears on Computex 2026 roadmap slides for 2029-2030. The cadence is not a marketing strategy. It is a procurement forcing function for data center operators who must plan power and cooling 24 months ahead of a rack landing.
Rubin Ultra (VR300) replaces the two-die Rubin package with a four-die configuration. Tom's Hardware confirmed it delivers 100 PFLOPS of FP4 inference per package and 1 TB of HBM4e per package at 32 TB/s bandwidth. Power consumption per package: approximately 3,600 watts. The rack configuration shifts from NVL72 to NVL576 — the "Kyber" rack — packing 576 GPU dies per rack targeting approximately 15 exaflops of FP4 inference and drawing around 600 kilowatts. Rubin Ultra was originally planned as a four-die configuration but has reportedly been scaled back to a dual-die design due to yield issues at TSMC's CoWoS-L advanced packaging with four-die interconnect bandwidth.
Feynman (2028), named after physicist Richard Feynman and paired with the Rosa CPU, introduces advanced 3D stacking technology, LP40 memory, BlueField-5 DPU, NVLink-8 interconnect, and what NVIDIA calls "custom HBM" — likely a derivative of HBM5 or a proprietary stack not yet defined publicly. Tweaktown's GTC 2026 coverage notes that Feynman's 3D stacking approach will increase density differently from the multi-die reticle strategy used in Rubin and Rubin Ultra.
Annual cadence at 600kW rack density means the facilities built for Rubin in 2026 may be undersized for Rubin Ultra in 2027. This is not hypothetical: the "stranded facility" problem — where data center capacity built at one power density spec is superseded before it earns back the capital invested in upgrading it — is already appearing in hyperscaler planning conversations. One industry analyst characterized it plainly at GTC 2026: they must be replanning before they are finished building.
The cadence works differently than it looks.
Geopolitics and the China Market
NVIDIA's share of China's AI chip market collapsed from roughly 95% in 2023 to effectively zero on new advanced GPU shipments by mid-2026, per Model Diplomat's analysis of the May 2026 BIS guidance. The Rubin GPU is entirely banned from export to China. Blackwell is banned. The Trump administration permitted H200 sales to China in January 2026 with significant volume caps and end-use monitoring requirements — a policy the Council on Foreign Relations characterized as strategically incoherent on its face, simultaneously acknowledging export risk and creating a pathway to permit sales.
Chinese firms, including DeepSeek, have reportedly obtained Blackwell chips through third-party intermediaries and shipment networks that dismantle servers in approved countries before importing components. The export control regime has not stopped Chinese AI development; it has accelerated domestic alternatives. CXMT is targeting viable HBM3 yields in 2026 and HBM3e by 2027. Huawei's Ascend 950DT was used to train DeepSeek V4. If domestic memory production closes even part of the gap, the performance ceiling of China's domestically available compute infrastructure rises in ways that current US policy did not account for.
For NVIDIA, the loss of China is absorbed by demand from hyperscalers elsewhere. Jensen Huang cited approximately $1 trillion in orders through 2027 at GTC 2026. NVIDIA's fiscal 2026 revenue reached $215.90 billion. The China market, once meaningful to quarterly results, has been priced out of the forward model entirely.
Who This Is For
Hyperscalers — AWS, Google Cloud, Microsoft Azure, Oracle Cloud, CoreWeave, Lambda, Nebius, and Nscale — already have confirmed Rubin allocations and the infrastructure required to receive them. They committed to liquid cooling investment two years ago. For them, this article describes what they have already purchased.
- Enterprise AI teams running production LLM inference at scale and already operating liquid-cooled data centers have a clear case for Rubin in H2 2026 or early 2027. The inference cost reduction for MoE models is real, and the CUDA compatibility story is straightforward — existing Blackwell code runs without recompilation.
- Organizations evaluating whether to build or rent compute for the next 18-24 months should be deeply skeptical of building. The Rubin to Rubin Ultra transition in 2027 will require facility upgrades that air-cooled and 48V-power-distributed facilities cannot accommodate without significant capital expenditure. Renting Rubin capacity from a cloud provider absorbs the cadence risk at the cost of margin.
- Research teams and AI startups with workloads under the 100-billion-parameter threshold should examine whether the Blackwell Ultra B300 — currently in volume production and offering 15 PFLOPS FP4 at 1,400W — meets their actual needs. Rubin's performance advantage is largest for MoE at long context. For smaller dense models and fine-tuning workloads, the performance-per-dollar calculation may favor staying on Blackwell infrastructure that already exists.
- Data center operators who have not yet begun liquid cooling infrastructure investment are facing a decision with a 6-to-12-month construction lead time. Starting now means Rubin availability in late 2027 at best — which lands close to Rubin Ultra. That timing may actually be optimal if facility specs can accommodate the 600 kW envelope, rather than building for 230 kW and retrofitting again in 18 months.
Verdict
Rubin delivers on the compute numbers. The 50 PFLOPS per GPU, 22 TB/s HBM4 bandwidth, and NVLink 6's 260 TB/s fabric are confirmed, not projected. The 10x inference cost reduction is real for MoE workloads at specific sequence lengths and narrower than the headline implies for everything else. The supply constraint is real — 200,000 to 300,000 units for 2026 versus demand visibility at $1 trillion through 2027. The infrastructure mandate is the genuine threshold: if your facility cannot accept liquid-cooled racks at 190-230 kilowatts, you are not deploying Rubin in 2026 regardless of your allocation.
The right procurement posture depends on one question: does your organization run workloads today that exhaust Blackwell B300 capacity, and do you have or can you build liquid cooling infrastructure within six months? If yes, Rubin is the correct platform and the transition is worth the capital. If no, Blackwell Ultra B300 still delivers meaningful throughput gains and does not require retrofitting your facility. The annual cadence is NVIDIA's real product — the architecture is the platform, the cadence is the subscription.
The unresolved tension at the edge of all this: AMD's Helios ships on 2nm with 432 GB of HBM4 per chip — 50% more memory per GPU than Rubin, at lower cost, with an open interconnect standard. If ROCm closes its compatibility gaps on frontier MoE frameworks over the next 12 months, the per-rack memory advantage could shift purchasing decisions at the workload tier where memory capacity, not compute throughput, is the actual constraint. NVIDIA's NVLink moat has never been seriously tested. Rubin is the first generation where the test conditions actually exist.
What is the NVIDIA Rubin GPU release date?
NVIDIA Rubin entered full production in Q1 2026 and volume shipments to customers are targeting the second half of 2026. Partner availability at AWS, Google Cloud, Microsoft Azure, Oracle Cloud, CoreWeave, Lambda, Nebius, and Nscale is confirmed, with first customer units expected by approximately August 2026 per statements from NVIDIA's manufacturing partners. Broad cloud instance availability is expected to follow into 2027.
How much faster is NVIDIA Rubin than Blackwell?
Rubin delivers 50 PFLOPS of FP4 inference per GPU versus Blackwell's approximately 10 PFLOPS — a 5x improvement per chip. At the rack level, the Vera Rubin NVL72 delivers 3.6 exaflops of FP4 inference versus Blackwell Ultra GB300 NVL72's 1.1 exaflops, a 3.3x improvement. NVIDIA claims up to 10x lower inference token cost, benchmarked on MoE models at specific sequence lengths — gains will vary significantly for dense model workloads.
Does NVIDIA Rubin require liquid cooling?
Yes, Rubin requires 100% liquid cooling with no air-cooled configuration available. Each Rubin GPU draws 1,800 to 2,300 watts and the VR200 NVL72 rack draws 190-230 kilowatts total. Data centers must deploy direct-to-chip liquid cooling before accepting Rubin systems. Retrofitting an air-cooled facility costs $500 to $1,500 per kilowatt and requires 6 to 12 months of construction work.
What is NVIDIA Rubin Ultra and when does it come out?
Rubin Ultra (VR300) is NVIDIA's planned successor to Rubin, targeted for the second half of 2027. It uses a dual-die (originally four-die) package delivering 100 PFLOPS of FP4 inference and 1 TB of HBM4e memory per GPU. The Kyber rack configuration targets approximately 15 exaflops per rack at around 600 kilowatts. Rubin Ultra deploys in the NVL576 rack format with up to 576 GPU dies.
NVIDIA Rubin vs AMD MI455X — which is better?
NVIDIA Rubin leads on FP4 compute (50 PFLOPS vs. 40 PFLOPS), memory bandwidth (22 TB/s vs. 19.6 TB/s), and scale-up interconnect bandwidth (260 TB/s NVLink 6 per rack vs. AMD's UALink-over-Ethernet in Helios V1). AMD's MI455X leads on raw memory capacity (432 GB vs. 288 GB per GPU) and costs roughly 30-35% less per chip. For MoE workloads where inter-GPU communication is the bottleneck, NVIDIA's interconnect advantage is likely more consequential. For workloads constrained by model memory rather than compute throughput, AMD's memory capacity advantage becomes meaningful.
What is NVIDIA Feynman and when does it come out?
Feynman is NVIDIA's GPU architecture planned for 2028, named after physicist Richard Feynman and paired with the Rosa CPU. Confirmed technology directions include advanced 3D stacking, LP40 memory, BlueField-5 DPU, and NVLink-8 interconnect. NVIDIA has described the memory as "custom HBM," which likely refers to a post-HBM4e generation. Detailed performance specifications have not been publicly disclosed.
Can you buy NVIDIA Rubin GPUs as a smaller company?
Direct allocation of Rubin GPUs in 2026 is reserved primarily for hyperscalers and large AI labs with established NVIDIA purchasing relationships. Smaller organizations will access Rubin through cloud providers once instance availability expands into 2027. Production is constrained to an estimated 200,000-300,000 units for full-year 2026, against demand orders exceeding $1 trillion through 2027. Cloud-based access is the realistic path for most teams outside the hyperscaler tier through at least mid-2027.